A multi-processor system is typically classified into the one of type SMP (Symmetric Multi-Processor) in which functions are homogeneously and symmetrically allocated to respective sub-processors, or into the one of type AMP (Asymmetric Multi-Processor) in which the functions are heterogeneously and asymmetrically allocated to the respective sub-processors.
In the multi-processor system of type AMP, a method where a main processor directly controls a plurality of other sub-processors has been traditionally used. This method is the one where the main processor, which manages the whole system to execute principal processing, also performs activation control of each of the sub-processors functionally distributed. The control over each sub-processor is performed by use of a system bus to which the main processor has the right of access. Each sub-processor inputs an interrupt signal to the main processor, and then the main processor checks the status of each sub-processor by using the system bus, whereby a process completion notification from each sub-processor is performed. Thus, it is possible to aggregate management of the status of the whole system and management of the status of each sub-processor in one place. Therefore, there are advantages of facilitating consideration and implementation of a control sequence in the whole multi-processor system, and of enhancing observability upon debug.
However, in the above-mentioned method, there is a problem that processing in the whole system LSI (Large Scale Integration) collapses due to the growing scale and complexity of the system LSI in recent years. The major factor is that, in the traditional architecture where the main processor performs the whole control, processing load concentrates in the main processor to be congested due to an increase in the number of sub-processors mounted in the system LSI.
There have been already proposed first to third related art for addressing this problem. Hereinafter, the first to third related art will be sequentially described.